The present disclosure generally relates to devices including at least one 2-dimensional carbon lattice structure, and particularly to field effect transistors including at least one 2-dimensional carbon lattice structure, and methods of manufacturing the same.
The ability to deposit a thin, pinhole-free gate dielectric on carbon nanostructures such as graphene and carbon nanotubes (CNTs) is important to enable the fabrication of field effect transistors with good electrostatics. However, the relative inertness of the channel material (lack of dangling bonds or chemically active sites) means that most gate dielectric materials and deposition techniques do not wet the surface of the nanostructure well.
In a first approach, a sufficient amount of dielectric material may be deposited until a surface of a graphene layer or a CNT is coated with a contiguous layer of the dielectric material. This approach results in overly thick gate dielectric films, however, because the nucleation on the graphene layer or the CNT proceeds in an island growth mode. In this approach, a continuous film is formed only after a thick enough material is deposited at a thickness greater than an optimal thickness range for the dielectric material as a gate dielectric.
In a second approach, the surface of a graphene layer or a CNT may be functionalized to make it more chemically active. Similarly, the surface of the graphene layer or the CNT may be slightly damaged through physical bombardment or plasma processes to create dangling bonds. Both of these surface treatments tend to enhance the effectiveness of an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process to be employed to deposit a dielectric material thereupon. However, this functionalization process reduces the quality of the channel material, reducing charge mobility and overall performance of the resulting FET.
In a third approach, deposition processes may be used in which the deposited species has very low energy, and thus cannot move around. For example, spin-on gate dielectrics may be used for this purpose. However, very thin films less than 10 nm in thickness are difficult to obtain with spin-on materials, and spin-on gate dielectrics tend to be of relatively low quality and contain a lot of trapped charges and impurities, resulting in devices with large hysteresis, poor subthreshold slope and poor repeatability.
In addition, graphene layers and carbon nanotubes are vulnerable to degradation from exposure to energetic oxygen species or plasma processes. Unfortunately, a large number of semiconductor processes, including plasma enhanced chemical vapor deposition (PECVD), reactive ion etching (RIE), and deposition of oxides by chemical vapor deposition (CVD) or physical vapor deposition (PVD), involve either energetic oxygen species or plasma processes. This greatly limits the number of microfabrication techniques that can be leveraged for the fabrication of graphene-based devices and CNT-based devices.